1. Field of Invention
The present invention relates to a semiconductor device and the fabrication method thereof. More particularly, the present invention relates to a memory device and the fabrication method thereof.
2. Description of Related Art
The flash memory device allows multiple and repetitive writing, reading and erasure operations, and the storage data are retained even after the power supply is discontinued. Because of the aforementioned advantages, the flash memory has become the mainstream non-volatile memory device, which is widely applied in the electronic products, such as, personal computers, digital cameras and personal digital assistants (PDAs) etc.
At present, the commonly adopted flash memory cell is composed of a stacked gate consisting of a floating gate and a control gate, a source/drain region and a select transistor disposed on one side of the stacked gate. FIG. 1 is a top view illustrating a prior art flash memory structure. Referring to FIG. 1, control gate line 114b, the floating gate (not shown), select gate line 115b and the source/drain region 116 constitute the first memory cell row 150, while control gate line 114a, the floating gate (not shown), select gate line 115a and the source/drain region 116 constitute the second memory cell row 160. The first memory cell row 150 and the neighboring second memory cell row 160 share a common source line 170 that is formed in the substrate 100 and in the active region 104 between two memory cell rows 150, 160.
Since an extra doping process is performed to the active region 104 of the substrate 100 to form the source line 170, the fabrication processes become more complicated and costly. Moreover, because the source line 170 is formed in the substrate 100, the source line 170 certainly occupies a certain area in the active region of the substrate 100. Besides, for every 16 to 32 bits, a contact 180 is needed in the conventional fabrication processes for reducing the resistance of the source line 170, of which the resistance increases as the length of the source line 170 extends. The contact 180 is connected to the metal line(s) above the source line 170, thus reducing the resistance of the source line 170. As mentioned above, the prior art flash memory structure usually occupies more chip areas and hinders high integration of the device.
Furthermore, corresponding to the source line 170 in the active region 104 of the substrate 100, the isolation structures 102 are formed as rectangle blocks in the design of the above flash memory structure. However, due to many uncontrollable factors of photolithography, corner rounding often occurs to the rectangle isolation structures 102 during the photolithography process. Once misalignment happens during defining the select gate lines 115a, 115b, the select gate line 115b is shifted to the dot line position 125b (as shown in dot line), covering the rounding corners of the isolation structures 102, which causes the channel length of the select gate 115b to become longer. On the other hand, the channel length of the select gate 115a remains constant because the position of the select gate 11a is not shifted. In this case, the memory cells in different rows will have unequal electrical properties. In order to solve such problems, a predetermined distance is preserved between the corners of the isolation structures and the select gate line for keeping the select gate line away from the corners in the design of the device. Nonetheless, the distance between two adjacent memory cells is increased, leading to consuming more chip areas and preventing the device from having higher level of integration.